Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. A gate oxide is typically formed from thermally grown silicon dioxide over a silicon substrate which is doped with either n-type or p-type dopants. For each MOS field effect transistor (MOSFET) being formed, a gate electrode is formed over the gate dielectric, and dopant impurities are then introduced into the semiconductor substrate to form source and drain regions. Many modern day semiconductor microelectronic fabrication processes form features having less than 0.25 micron critical dimensions, for example more recent devices include features sizes of less than 0.13 microns. As design rules decrease, the size of a resulting transistor as well as transistor features, for example gate length, also decrease according to scaling relationships. As gate lengths decrease, the problem of current leakage, for example gate induced drain leakage (GIDL) becomes more severe, which is a problem for low power devices, requiring increased transistor off current.
In order to overcome this phenomenon, an increasing trend in semiconductor microelectronic device fabrication is to use high-K (high dielectric constant materials) in the gate dielectric stack to achieve an equivalent oxide thickness (EOT) with thicker high-K materials. Because of high tunneling currents, SiO2 films thinner than about 20 Angstroms cannot be reliably used as gate dielectrics in CMOS devices. There are currently intense efforts to replace traditional SiO2 gate dielectric films with high-K dielectric materials. A high dielectric constant allows a thicker gate dielectric to be formed which dramatically reduces tunneling current and consequently gate leakage current, thereby overcoming a severe limitation in the use of SiO2 as the gate dielectric at smaller device critical dimensions.
There have been, however, difficulties in forming high-k gate dielectrics to achieve acceptable threshold Voltage behavior in CMOS devices. Frequently, a relatively large shift in flatband Voltage or equivalent threshold Voltage occurs when high-K dielectrics are used in a gate dielectric stack for both NMOS and PMOS devices. For example, hafnium oxide (e.g., HfO2) when used in the gate dielectric stack exhibits a shift of from about 300 mV in NMOS devices and about 700 mV in PMOS devices compared to a conventional SiO2 gate dielectric.
The presence of unwanted interfacial states is believed to contribute to flatband and threshold Voltage shifts. Several approaches, from treating the base oxide layer, to post deposition annealing of the high-K dielectric prior to polysilicon electrode layer deposition have been proposed. Proposed approaches so far have met with limited success, threshold Voltages still exhibiting larges differences compared to normal or desired behavior achieved with conventional SiO2 gate dielectrics. As a result, the integration of high-K gate dielectric stacks with acceptable electrical behavior including acceptable threshold Voltage behavior in low power CMOS devices remains a problem to be overcome.
Therefore it would be advantageous to develop an improved method for forming gate structures including high-K dielectric layer stacks in CMOS devices having improved electrical performance including threshold Voltage performance.
It is therefore an object of the invention to provide an improved method for forming gate structures including high-K dielectric layer stacks in CMOS devices having improved electrical performance including threshold Voltage performance, while overcoming other shortcomings and deficiencies of the prior art.